AnalogML™ — inference before the ADC.
Digital AI spends most of its energy outside of inference computation — converting, buffering, and shuffling data to & from memory. AnalogML works on the signal itself, in the analog domain, and only wakes the digital system when something matters.
Most of digital AI's power is spent outside of inference.
A conventional always-on system digitizes every sample of a signal, then runs it through a DSP or accelerator — whether or not anything is happening. That constant conversion and data movement is where the energy goes.
AnalogML processes the signal as a waveform, before the ADC. It performs always-on detection and classification directly on the analog signal, waking the power-hungry digital system only on an event of interest. The result is always-on AI under 20µA — far less than the 2–5mA of a traditional digital always-on path.
One core, any analog signal or signals (fusion).
Because AnalogML works on the waveform itself, it isn't tied to one kind of sensor or a single sensor. The same core detects the signatures that matter across domains.
As well as pressure, current, and other continuous-signal modalities. If it's an analog signal, the core can learn it.
Analog performance, without analog expertise.
AnalogML is software-programmable: define and train models in Python and PyTorch, deploy through the Aspinity SDK, no analog or firmware expertise required.
That programmability turns a novel device into a platform. The same silicon can be configured for drone detection, machine anomaly detection, or vehicle security, and retuned in the field as models improve.
Production silicon, backed by years of R&D.
AML100 is shipping and being designed in today; AML200 extends the same architecture to RF. Behind these are decades of AnalogML development and a broad patent portfolio that addresses the variability and repeatability challenges assumed with analog circuitry.
The hard problems in analog, solved and protected.
Analog computing has long been dismissed as impractical — too sensitive to process variation, too difficult to program, too hard to reproduce at scale. Aspinity's patent portfolio exists because we solved those problems.
Built on decades of R&D, our IP covers the RAMP™ reconfigurable analog architecture, the co-located analog memory that stores parameters at the compute circuit, and the variation-trimming methods that make analog silicon repeatable in volume production.
18 granted patents13 pending12 patent families
What the portfolio covers
- ArchitectureRAMP™ — the reconfigurable analog modular processor that brings digital-like programmability into the analog domain.
- MemoryAnalog memory co-located in the compute circuits, storing parameters at 10+ bits of precision with no memory fetch.
- VariationSoftware-driven trimming that corrects for manufacturing and environmental variation, historically the barrier to production analog compute.
- ProgrammabilityField-programmable analog signal chains, configured from standard ML tooling rather than analog design.
Every alternative trades power for edge AI performance.
| Aspinity | Digital MCU + DSP | Digital neural accel. | Analog in-memory |
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Representative categories, not exhaustive. Figures reflect typical always-on continuous-inference operation.
Want the technical detail?
We're happy to walk through the architecture, the SDK, and how AnalogML maps to your signal and your power budget.