If it seems like all your mobile devices are getting smarter by the minute, you’re right. It’s not just that designers are squeezing more sensors into every square millimeter of board space, although that helps. It’s more due to the growing availability of small, low-power processors that can handle machine learning (ML) and AI tasks that previously required tons of computing power. While it’s no easy feat to compress and run large neural networks in power- and size-constrained devices — think about wearables/hearables and TV remotes — tech companies are making significant progress in doing just that.
At last month’s tinyML Summit
, Aspinity joined other industry thought leaders, including Qualcomm, Samsung, Google, and Arm, to explore the size and power challenges of using tinyML to extract intelligence from the physical world. Eliminating the bottlenecks in developing a power- and size-optimized neural network through more efficient algebraic functions and memory access was a big part of the conversation. There was also a collective buzz on establishing industry benchmarks for comparing the energy efficiency of the digital cores that comprise today’s tinyML chips.
At Aspinity, we’re looking beyond just enhancing power efficiency in digital cores (and in sensors) as we work to tackle the power/size issues. We think the best way to bring tinyML and AI to small, smart electronic devices is to consider the average power of the entire edge processing system, rather than just comparing one chip to another.
Start at the beginning (of the signal chain)
All sensed data is naturally analog. Yet we take all the data, relevant or not, and process it downstream in a digital core. Depending on the application, we might spend 80-90% of the time (and battery power) processing irrelevant data that will simply be thrown away. So, right at the beginning of the signal chain, we’re already inefficient.
At Aspinity, we take a different tack. We combine the inherent low-power properties of analog with the power of machine learning to determine which data are important up front, before the data are digitized. There’s no sending irrelevant data to the power-hungry DSP right from the get-go.
In our tinyML poster session (see poster here
), we presented a bio-inspired shift from the conventional “digitize-first” architecture to an “analyze-first” architecture using our ultra-low power, programmable analog ML core: RAMP.
The RAMP IC adds a new abstraction layer into the always-on system, determining very early which data are important – similar to the way our brains operate very efficiently with early filtering. It’s easy, for example, for us to differentiate a dog bark from a person’s voice. That’s because our brains do the analysis up front as the sound enters our ear and doesn’t waste energy trying to interpret words in the dog bark.
In the Aspinity system architecture, the RAMP chip keeps the ADC and higher-power processors asleep until it detects an event in the raw analog sensor data. That’s how we eliminate the wasteful downstream digitization and analysis of irrelevant data, and it is why RAMP-based systems are vastly more power- and size-efficient than the old “digitize-first” systems.
Detecting events earlier in the signal chain when the sensor data is still analog — and keeping the rest of the system asleep until important data are detected — changes the way system designers can think about comparing the energy efficiency of edge-processing solutions.
While it’s still important to compare the chip-to-chip performance parameters of the microcontroller or the DSP, the battery lifetime of the always-on device is much more affected by the volume of data that the digital core has to analyze in the first place. So, if we want to more accurately compare edge-processing solutions, we need to start at the sensor input and consider how long the ADC and digital core stay on over the course of a day. That’s the best way to determine the average energy consumption and battery lifetime per charge.
As an example, let’s look at a voice-first remote control where a RAMP IC enables ultra-low power analog voice activity detection (VAD). Statistically, we know voice is generally present for ~20% of the time. For the other 80% of the time when no voice is present, it’s a waste for the wake word engine to actively analyze sound. Rather, we keep the ADC and the microprocessor/DSP hosting the wake word engine off — or in a low-power sleep mode — until the system needs them. When the RAMP chip detects voice in the analog microphone signal, it wakes up the downstream system to listen for a wake word and additional commands. The result is a voice-first remote that uses up to 10x less power in the course of a day, extending battery life by many months when compared to a traditional digitize-first system.
We all want smarter mobile devices, but not at the expense of battery life. While some may think that analog is an old, outdated technology that’s hard to master, we and others in the tinyML community believe that analog is the key to a successful tinyML future. An analog neural network delivers the same high performance but in lower power than digital. That means we’ll have more intelligent mobile devices that run longer on a single charge (or battery) than we’ve ever imagined. And as long as we make analog chips with machine learning as easy to program as a microcontroller or a DSP — which is what we do with the RAMP chip — we can give designers all the benefits of tinyML in a broad range of edge-processing solutions, from smart earbuds and IoT devices to smart home systems.
Interested in learning how the RAMP IC can help in your design?