It’s no secret that the performance of analog circuits is susceptible to physical process variations that naturally occur during CMOS wafer manufacturing. And this has made it difficult to manufacture complex, large-scale analog chips with a high level of predictability and repeatability. By contrast, digital electronics offers both a high level of functionality and an immunity to process variations and can, if needed, be trimmed rather easily with software. It’s no surprise then, that complex edge processing chips are almost entirely digital, even in cases where an equivalent calculation can be done in analog in fewer steps and using less power.
Fortunately, there is a way to leverage the power-saving benefits of analog without exposing the performance to the process variations from CMOS manufacturing. Aspinity’s analogML™ core
is a fully analog machine learning chip that pulls inferencing into the analog domain. It may sound too difficult to overcome process variations such as offsets, temperature drifts, or the precise bias control required for such a sophisticated analog processor. However, the analogML core is comprised of multiple analog circuit blocks, which can each be fully synthesized and configured with software
. This previously unheard-of level of flexibility for analog circuitry makes the analogML core unique among analog chips and it’s why a single analogML core can run different algorithms to support a wide range of always-on applications.
The same hardware innovations (read more about our RAMP™ technology platform
on which the analogML core is designed) that allow the use of software to set parameters such as the bandwidth of the filters and the weights of the neural network in the analogML core also enable the trimming of offsets and other variables that are impacted by physical process variations from the standard CMOS fabrication process. The analogML core brings the predictability and reliability of digital processors into analog by addressing functionality and process variations with software.
So, while typical analog circuitry still suffers from repeatability challenges due to process variations, you now realize that the analogML core is not typical analog. Because it can be trimmed in software as you would do with a digital chip, the analogML core alleviates concerns about analog’s unpredictability, enabling its use in high volume edge processing applications where it can deliver superior data- and power-efficiency for the entire system.
Learn more about the analogML™ core
Learn more about Aspinity's RAMP™ technology platform
for more information about integrating the analogML core into your design and start saving power today.